1. Field of the Invention
This invention relates to the testing of memory arrays and, more particularly, to an apparatus and method for self-testing of a memory array embedded in a large scale integrated (LSI) circuit of the type utilized in digital computers and the like.
2. Description of the Prior Art
Methods and apparatus for testing memory arrays and, in particular, embedded arrays are disclosed in the following U.S. Patents:
U.S. Pat. No. 3,751,649, issued Aug. 7, 1973, and entitled "Memory System Exerciser".
U.S. Pat. No. 3,781,670, issued Dec. 25, 1973, and entitled "AC Performance Test for Large Scale Integrated Circuit Chips".
U.S. Pat. No. 3,781,683, issued Dec. 25, 1973, and entitled "Test Circuit Configuration for Integrated Semiconductor Circuits and a Test System Containing Said Configuration".
U.S. Pat. No. 3,789,205, issued Jan. 29, 1974, and entitled "Method of Testing Mosfet Planar Boards".
U.S. Pat. No. 3,790,885, issued Feb. 5, 1974, and entitled "Serial Test Patterns for Mosfet Testing".
U.S. Pat. No. 3,849,872, issued Nov. 26, 1974, and entitled "Contacting Integrated Circuit Chip Terminal Through the Wafer Kerf".
U.S. Pat. No. 3,924,144, issued Dec. 2, 1975, and entitled "Method for Testing Logic Chips and Logic Chips Adapted Therefor".
U.S. Pat. No. 3,961,251, issued June 1, 1976, and entitled "Testing Embedded Arrays".
U.S. Pat. No. 3,961,252, issued June 1, 1976, and entitled "Testing Embedded Arrays".
U.S. Pat. No. 3,961,254, issued June 1, 1976, and entitled "Testing Embedded Arrays".
U.S. Pat. No. 4,074,851, issued Feb. 21, 1978, and entitled "Method of Level Sensitive Testing a Functional Logic System with Embedded Array".
Thus, even though the problem of testing embedded arrays has been addressed in the past, none of the prior art solutions permits performance testing, disturb testing and diagnostic testing, while at the same time permitting a wide variety of test patterns to be applied to the array while the array is still embedded.